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FDD3672
June 2002
FDD3672
N-Channel UltraFET(R) Trench MOSFET 100V, 44A, 28m
Features
* r DS(ON) = 24m (Typ.), VGS = 10V, ID = 44A * Qg(tot) = 24nC (Typ.), VGS = 10V * Low Miller Charge * Low Qrr Body Diode * Optimized efficiency at high frequencies * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101 * High Voltage Synchronous Rectifier * Direct Injection / Diesel Injection System * 42V Automotive Load Control * Electronic Valve Train System
Formerly developmental type 82760
Applications
* DC/DC converters and Off-Line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V Systems
DRAIN (FLANGE) GATE SOURCE
D
G
TO-252AB
FDD SERIES
S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, R JA = 52oC/W) Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 44 31 6.5 Figure 4 120 135 0.9 -55 to 175 A A A A mJ W W/oC
o
Ratings 100 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252 Thermal Resistance Junction to Ambient TO-252, 1in copper pad area
2
1.11 100 52
o o o
C/W C/W C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2002 Fairchild Semiconductor Corporation FDD3672 Rev. A
FDD3672
Package Marking and Ordering Information
Device Marking FDD3672 Device FDD3672 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 80V VGS = 0V VGS = 20V TC= 150oC 100 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance V GS = VDS, ID = 250A ID = 44A, VGS = 10V ID = 21A, VGS = 6V, ID=44A, VGS=10V, TC=175oC 2 0.024 0.031 0.054 4 0.028 0.047 0.068 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 50V ID = 44A Ig = 1.0mA 1710 247 62 24 3 8.6 5.6 5.6 36 4.5 pF pF pF nC nC nC nC nC
Resistive Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 44A VGS = 10V, RGS = 11.0 11 59 26 44 104 104 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovery Charge ISD = 44A ISD = 21A ISD = 44A, dISD/dt =100A/s ISD = 44A, dISD/dt =100A/s 1.25 1.0 52 80 V V ns nC
Notes: 1: Starting TJ = 25C, L = 0.6mH, IAS = 20A. 2: Pulse Width = 100s
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
Typical Characteristics TC = 25C unless otherwise noted
1.2 50 VGS = 10V
POWER DISSIPATION MULTIPLIER
1.0 40 0.8 ID, DRAIN CURRENT (A) 0 25 50 75 100 125 150 175 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) 175 TC , CASE TEMPERATURE (oC) 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 0.01 10-5 10-4
30
0.6
20
0.4
0.2
10
0
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
Figure 3. Normalized Maximum Transient Thermal Impedance
500 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
VGS = 10V
I = I 25
175 - TC 150
100
30 10 -5 10-4 10-3 10-2 t , PULSE WIDTH (s) 10-1 100 10 1
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
Typical Characteristics TC = 25C unless otherwise noted
300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID , DRAIN CURRENT (A) 80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
IAS, AVALANCHE CURRENT (A)
100
60
STARTING TJ = 25oC 10 150oC
TJ = 175 oC 40 TJ = 25o C 20 TJ = -55oC
STARTING TJ =
1 0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10
0 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V) 6.5
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching Capability
80 VGS = 10V VGS = 7V VGS = 6V DRAIN TO SOURCE ON RESISTANCE (m ) TC = 25oC 60 40
Figure 6. Transfer Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 35 VGS = 6V 30
ID, DRAIN CURRENT (A)
40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 20 VGS = 5V 0 0 0.5 1.0 1.5 2.0 2.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 3.0
25
VGS = 10V
20
15 0 10 20 30 ID, DRAIN CURRENT (A) 40 50
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Drain Current
1.2
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 NORMALIZED GATE THRESHOLD VOLTAGE
VGS = VDS, ID = 250A 1.0
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
1.5
0.8
1.0 VGS = 10V, ID = 44A 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200
0.6
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (o C) 200
Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature
FDD3672 Rev. A
FDD3672
Typical Characteristics TC = 25C unless otherwise noted
1.2 ID = 250A 3000 CISS = CGS + CGD COSS CDS + CGD
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1000 1.1 C, CAPACITANCE (pF)
C RSS = CGD 100
1.0
VGS = 0V, f = 1MHz 0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) 200 10 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100
Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VDD = 50V VGS , GATE TO SOURCE VOLTAGE (V) 8
Figure 12. Capacitance vs Drain to Source Voltage
6
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 44A ID = 21A 0 5 10 15 20 25
0 Qg, GATE CHARGE (nC)
Figure 13. Gate Charge Waveforms for Constant Gate Currents
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT) VDS
L VGS = 10V VGS
+
VDD DUT Ig(REF) 0 Qg(TH)
VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P D M = ----------------------------R JA
125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 100 RJA (oC/W) RJA = 33.32+ 154/(1.73+Area) EQ.3
75
(EQ. 1)
50
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA
25 0.01 (0.0645)
0.1 (0.645)
1 (6.45)
10 (64.5)
AREA, TOP COPPER AREA in2 (cm2)
Figure 20. Thermal Resistance vs Mounting Pad Area
= 33.32 + ------------------------------------
23.84 ( 0.268 + Area )
(EQ. 2)
Area in Inches Squared
R
JA
= 33.32 + ---------------------------------
154 ( 1.73 + Area )
(EQ. 3)
Area in Centimeters Squared
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
PSPICE Electrical Model
.SUBCKT FDD3672 2 1 3 ; CA 12 8 5.8e-10 Cb 15 14 6.8e-10 Cin 6 8 1.6e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 105 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 9.56e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.45e-9 RLgate 1 9 95.6 RLdrain 2 5 10 RLsource 3 7 44.5 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 6.0e-3 Rgate 9 20 1.5 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 9.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))} .MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6 + CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0) .MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60) .MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5) .MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1) .MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7) .MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6) .MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
GATE 1 RLGATE CIN
rev May 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
(c)2002 Fairchild Semiconductor Corporation
+
DBODY
FDD3672 Rev. A
FDD3672
SABER Electrical Model
REV May 2002 template FDD3672 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0) dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6) dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60) m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1) LDRAIN m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1) DPLCAP 5 DRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5) 2 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10 RLDRAIN sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3) RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5) 51 RSLC2 c.ca n12 n8 = 5.8e-10 ISCL c.cb n15 n14 = 6.8e-10 c.cin n6 n8 = 1.6e-9
50 DBREAK
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
LGATE
ESG + EVTEMP RGATE + 18 22 9 20
6 8
RDRAIN EVTHRES + 19 8 6 MSTRO CIN 8 21 16
11 DBODY MWEAK
spe.ebreak n11 n7 n17 n18 = 105 GATE 1 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1
MMED
RLGATE
EBREAK + 17 18 -
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 12 13 8 S1B CA 13 + 6 8 S2A 14 13 S2B CB + EDS 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
l.lgate n1 n9 = 95.6e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.45e-9 res.rlgate n1 n9 = 9.56 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 44.5
EGS
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7 res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5 res.rgate n9 n20 = 1.5 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3)) }
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
FDD3672
SPICE Thermal Model
REV May 2002 FDD3672 CTHERM1 TH 6 3.2e-3 CTHERM2 6 5 3.3e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 3.5e-3 CTHERM5 3 2 6.4e-3 CTHERM6 2 TL 1.9e-2 RTHERM1 TH 6 5.5e-4 RTHERM2 6 5 5.0e-3 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 10.5e-2 RTHERM5 3 2 3.4e-1 RTHERM6 2 TL 3.5e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDD3672 template thermal_model th tl thermal_c th, tl { cctherm.ctherm1 th 6 =3.2e-3 ctherm.ctherm2 6 5 =3.3e-3 ctherm.ctherm3 5 4 =3.4e-3 ctherm.ctherm4 4 3 =3.5e-3 ctherm.ctherm5 3 2 =6.4e-3 ctherm.ctherm6 2 tl =1.9e-2 rtherm.rtherm1 th 6 =5.5e-4 rtherm.rtherm2 6 5 =5.0e-3 rtherm.rtherm3 5 4 =4.5e-2 rtherm.rtherm4 4 3 =10.5e-2 rtherm.rtherm5 3 2 =3.4e-1 rtherm.rtherm6 2 tl =3.5e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2002 Fairchild Semiconductor Corporation
FDD3672 Rev. A
TRADEMARKS
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SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET(R) VCXTM
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 2. A critical component is any component of a life support As used herein: device or system whose failure to perform can be 1. Life support devices or systems are devices or systems reasonably expected to cause the failure of the life support which, (a) are intended for surgical implant into the body, device or system, or to affect its safety or effectiveness. or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2002 Fairchild Semiconductor Corporation
Rev. H7

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